`timescale 1ns/1ns
module fdiv1_8_test;
  reg clk;
  reg rst;
  reg [3:0]N;
  wire clk_out;
  wire [3:0] m,n,k;
  wire COUT1,COUT2,COUT3;
fdiv1_8 u1(clk,rst,N,clk_out);
always #5 clk=~clk;

initial begin
  clk=0;rst=0;N=3;
  #10 rst=1;
  #120
  #10 rst=0;
  #10 rst=1;
  #10 N=5;
  #120 $stop;
end

initial $monitor($time, , ,"clk=%b rst=%b N=%d COUT1=%b COUT2=%b COUT3=%b clk_out=%b",clk,rst,N,COUT1,COUT2,COUT3,clk_out);
endmodule
